Electrical Engineering-Systems Dept.

*** SEMINAR ***

Rami Zecharia

(M.Sc. student under the supervision of Prof. Yair Be’ery)

on the subject:

Parallel Programmable Scheduler Towards Application-Specific Many-Core Architectures

A scheduler function is a crucial building block within the Traffic Manager (TM) in switches/routers. It is responsible for scheduling data from back-logged queues to output ports. The features and requirements of the scheduler function are changed often by ISPs (Internet Service Provides) due to the changes in the usage of the Internet and the ever-growing need for more bandwidth. This forces vendors to develop new TM devices too often. Due to high design and production costs a software based schedulers are desirable.

Programmable scheduler implemented on a single core does not provide sufficient performance as compared to hardware based schedulers. This thesis presents a method for parallel programmable scheduler to be executed in many-core systems with similar performance, power and silicon price as hardware based solution.

The parallel programmable scheduler algorithm was tested on the unique Plurality HyperCore architecture that is different from the standard 2D grid. Simulation results show that the achieved performance is not deterministic but depends on various factors such as the architecture, the database and the parameters set by ISPs.

The un-deterministic performance and the quest for higher bandwidth lead to the presentation of a new and dedicated, application specific, architecture. This new architecture is optimally tuned for the scheduling function in order to achieve high and deterministic performance which is independent of the scheduling database and with power and silicon cost similar to hardware based solutions.