Electrical Engineering-Systems Dept.

*** SEMINAR ***

Aleksei Jolondz

(M.Sc. under the supervision of Prof. Shlomo Weiss and Dr. Amit Golander)

on the subject:

Leveraging 3D IC Technology to Design Multicore Compute Clusters with Identical Layers

The present tendency to increase the number of cores in multicore compute clusters leads to significant growth in the length of the on-chip interconnects. Particularly, the L1-L2 interconnect, which has low latency requirements, gets very long because it has to extend over the large physical size of the cores and multiple L2 cache banks. Usage of private instead of shared L2 cache does not efficiently utilize L2 memory when cores have different memory demand. Three dimensional integrated circuits technology (3D IC) is one of the possible solutions for the wire length problem.

We introduce a novel 3D implementation of the interconnect between cores and shared L2 cache banks for multicore clusters. The 3D structure extends cluster sizes that can be supported with tolerable wire delays. The emphasis is on improving performance as a result of shorter connections achieved by splitting existing 2D design into four layers. The splitting enables implementation of a better arbitration scheme, which leads to additional performance improvement. The simulations show improvement of the average memory access time (AMAT) by 9.1 cycles, improvement of performance by 5.6%, and power reduction by 12%. In addition, decreasing of design and manufacturing cost is achieved by using identical layers.