Lecture Slide
| Chapters 1-11 (from Digital Abstraction till
Additional Components) |
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pdf |
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| Chapter 1: The digital abstraction |
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pdf |
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| Chapter 2: Foundations of combinational
circuits |
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pdf |
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| Chapter 3: Trees |
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pdf |
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| Chapter 4: Decoders and Encoders |
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pdf |
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| Chapter 4: addendum |
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pdf |
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| Chapter 5: Selectors, shifters, P-ENCS,
H-Dec |
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pdf |
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| Chapter 6: Addition |
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pdf |
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| Chapter 7: Fast Addition |
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pdf |
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| Chapter 8: Signed Addition |
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pdf |
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| Chapter 9: Flip-Flops |
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pdf |
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| Chapter 10: Synchronous Circuits |
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pdf |
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| Chapter 11: Additional Components |
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pdf |
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| Static RAM by Randy Katz |
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| The general purpose machine by Heuring &
Jordan |
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| Chapter 2: Machines, Machine Languages,
and Digital Logic by Heuring & Jordan |
ppt |
pdf |
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| The simplified DLX - part 1 |
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| Simplified DLX instruction set |
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| The simplified DLX - part 2 |
ppt |
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| The simplified DLX - a few environments
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ppt |
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Exercise Slides
| Exercise 1: Boolean Algebra |
ppt |
pdf |
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| Exercise 2: Boolean algebra cont' + The
digital abstraction |
ppt |
pdf |
pdf,
4 slides per page |
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| Exercise 3: Foundations of combinational circuits |
ppt |
pdf |
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| Exercise 4: Decoders and Trees |
ppt |
pdf |
pdf, 4
slides per page |
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| Exercise 5: Encoders, Decoders and Shifters |
ppt |
pdf |
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| Note on Proving Lower Bounds of Cost &
Delay |
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pdf |
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| Exercise 6: U-PENCs, B-PENCs and Half-Decoders |
ppt |
pdf |
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| Exercise 7: Addition |
ppt |
pdf |
pdf, 4 slides
per page |
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| Exercise 8: Parallel Prefix Computation |
ppt |
pdf |
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| Exercise 9: Signed Addition |
ppt |
pdf |
pdf, 4 slides
per page |
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| Exercise 10: Flip-Flops |
ppt |
pdf |
pdf, 4 slides
per page |
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| Exercise 11: Synchronous Circuits |
ppt |
pdf |
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| Exercise 12: DLX Assembly language |
ppt |
pdf |
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| Exercise 13: DLX Processor |
ppt |
pdf |
pdf, 4 slides
per page |
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