*------------------------------------------------------------------* * Example of a test program for the DLX *------------------------------------------------------------------* * * Test0: Fetch / Addresses / Jump Register * Test1: Databus of RESA-Bus * Test2: ALU: AddI * Test3: Shifter * Test4: Registerfile * Test5: ALU: Add * Test6: ALU: Or, And, Xor, TestSet * Test7: Branch / JALR * Test8: RAM Test (optional) * *------------------------------------------------------------------* *------------------------------------------------------------------* * Test0: Fetch / Addresses / Jump Register *------------------------------------------------------------------* pc = 0x00000000 test0: dc 0xc0000000 * Special-Nop nop * == addi R0 R0 0x0 nop nop nop nop nop nop nop nop nop nop nop nop nop nop lw R1 R0 adr1 jr R1 error0: beqz R0 error0 *------------------------------------------------------------------* * Variables *------------------------------------------------------------------* pc = 0x00000020 bit0: dc 0x00000001 bit1: dc 0x00000002 bit2: dc 0x00000004 bit3: dc 0x00000008 bit4: dc 0x00000010 bit5: dc 0x00000020 bit6: dc 0x00000040 bit7: dc 0x00000080 bit8: dc 0x00000100 bit9: dc 0x00000200 bit10: dc 0x00000400 bit11: dc 0x00000800 bit12: dc 0x00001000 bit13: dc 0x00002000 bit14: dc 0x00004000 bit15: dc 0x00008000 bit16: dc 0x00010000 bit17: dc 0x00020000 bit18: dc 0x00040000 bit19: dc 0x00080000 bit20: dc 0x00100000 bit21: dc 0x00200000 bit22: dc 0x00400000 bit23: dc 0x00800000 bit24: dc 0x01000000 bit25: dc 0x02000000 bit26: dc 0x04000000 bit27: dc 0x08000000 bit28: dc 0x10000000 bit29: dc 0x20000000 bit30: dc 0x40000000 bit31: dc 0x80000000 null: dc 0x00000000 mask0: dc 0x00000000 mask8: dc 0x000000ff mask16: dc 0x0000ffff mask24: dc 0x00ffffff mask32: dc 0xffffffff maska5: dc 0xa5a5a5a5 mask5a: dc 0x5a5a5a5a adr0: dc test0 adr1: dc test1 adr2: dc test2 adr3: dc test3 adr4: dc test4 adr5: dc test5 adr6: dc test6 adr7: dc test7 adr8: dc test8 RESA: dc 0x52455341 * "RESA" USER: dc 0x00800001 * Start addresse of user program RAM: dc 0x00800000 ramadr: dc 0x00800000 ramend: dc 0x00900000 *------------------------------------------------------------------* * Test1: Databus of RESA-Bus *------------------------------------------------------------------* pc = 0x00000100 test1: dc 0xc0000001 * Special-NOP lw R1 R0 bit0 lw R1 R0 bit1 lw R1 R0 bit2 lw R1 R0 bit3 lw R1 R0 bit4 lw R1 R0 bit5 lw R1 R0 bit6 lw R1 R0 bit7 lw R1 R0 bit8 lw R1 R0 bit9 lw R1 R0 bit10 lw R1 R0 bit11 lw R1 R0 bit12 lw R1 R0 bit13 lw R1 R0 bit14 lw R1 R0 bit15 lw R1 R0 bit16 lw R1 R0 bit17 lw R1 R0 bit18 lw R1 R0 bit19 lw R1 R0 bit20 lw R1 R0 bit21 lw R1 R0 bit22 lw R1 R0 bit23 lw R1 R0 bit24 lw R1 R0 bit25 lw R1 R0 bit26 lw R1 R0 bit27 lw R1 R0 bit28 lw R1 R0 bit29 lw R1 R0 bit30 lw R1 R0 bit31 lw R1 R0 adr2 jr R1 *------------------------------------------------------------------* * Test2: ALU: AddI *------------------------------------------------------------------* pc = 0x00000200 test2: dc 0xc0000002 * Special-NOP addi R1 R0 0x0001 addi R1 R0 0x0002 addi R1 R0 0x0004 addi R1 R0 0x0008 addi R1 R0 0x0010 addi R1 R0 0x0020 addi R1 R0 0x0040 addi R1 R0 0x0080 addi R1 R0 0x0100 addi R1 R0 0x0200 addi R1 R0 0x0400 addi R1 R0 0x0800 addi R1 R0 0x1000 addi R1 R0 0x2000 addi R1 R0 0x4000 addi R1 R0 0x8000 lw R1 R0 adr3 jr R1 *------------------------------------------------------------------* * Test3: Shifter *------------------------------------------------------------------* pc = 0x00000300 test3: dc 0xc0000003 * Special-NOP lw R1 R0 bit0 slli R1 R1 slli R1 R1 slli R1 R1 slli R1 R1 slli R1 R1 slli R1 R1 slli R1 R1 slli R1 R1 slli R1 R1 slli R1 R1 slli R1 R1 slli R1 R1 slli R1 R1 slli R1 R1 slli R1 R1 slli R1 R1 slli R1 R1 slli R1 R1 slli R1 R1 slli R1 R1 slli R1 R1 slli R1 R1 slli R1 R1 slli R1 R1 slli R1 R1 slli R1 R1 slli R1 R1 slli R1 R1 slli R1 R1 slli R1 R1 slli R1 R1 slli R1 R1 lw R1 R0 bit31 srli R1 R1 srli R1 R1 srli R1 R1 srli R1 R1 srli R1 R1 srli R1 R1 srli R1 R1 srli R1 R1 srli R1 R1 srli R1 R1 srli R1 R1 srli R1 R1 srli R1 R1 srli R1 R1 srli R1 R1 srli R1 R1 srli R1 R1 srli R1 R1 srli R1 R1 srli R1 R1 srli R1 R1 srli R1 R1 srli R1 R1 srli R1 R1 srli R1 R1 srli R1 R1 srli R1 R1 srli R1 R1 srli R1 R1 srli R1 R1 srli R1 R1 srli R1 R1 lw R1 R0 adr4 jr R1 *------------------------------------------------------------------* * Test4: Registerfile *------------------------------------------------------------------* pc = 0x00000400 test4: dc 0xc0000004 * Special-NOP addi R0 R0 0 addi R1 R0 1 addi R2 R0 2 addi R3 R0 3 addi R4 R0 4 addi R5 R0 5 addi R6 R0 6 addi R7 R0 7 addi R8 R0 8 addi R9 R0 9 addi R10 R0 10 addi R11 R0 11 addi R12 R0 12 addi R13 R0 13 addi R14 R0 14 addi R15 R0 15 addi R16 R0 16 addi R17 R0 17 addi R18 R0 18 addi R19 R0 19 addi R20 R0 20 addi R21 R0 21 addi R22 R0 22 addi R23 R0 23 addi R24 R0 24 addi R25 R0 25 addi R26 R0 26 addi R27 R0 27 addi R28 R0 28 addi R29 R0 29 addi R30 R0 30 addi R31 R0 31 addi R0 R0 0x0 addi R1 R1 0x0 addi R2 R2 0x0 addi R3 R3 0x0 addi R4 R4 0x0 addi R5 R5 0x0 addi R6 R6 0x0 addi R7 R7 0x0 addi R8 R8 0x0 addi R9 R9 0x0 addi R10 R10 0x0 addi R11 R11 0x0 addi R12 R12 0x0 addi R13 R13 0x0 addi R14 R14 0x0 addi R15 R15 0x0 addi R16 R16 0x0 addi R17 R17 0x0 addi R18 R18 0x0 addi R19 R19 0x0 addi R20 R20 0x0 addi R21 R21 0x0 addi R22 R22 0x0 addi R23 R23 0x0 addi R24 R24 0x0 addi R25 R25 0x0 addi R26 R26 0x0 addi R27 R27 0x0 addi R28 R28 0x0 addi R29 R29 0x0 addi R30 R30 0x0 addi R31 R31 0x0 lw R1 R0 adr5 jr R1 *------------------------------------------------------------------* * Test5: ALU: Add *------------------------------------------------------------------* pc = 0x00000500 test5: dc 0xc0000005 * Special-NOP addi R2 R0 0x0 lw R1 R0 bit0 add R2 R2 R1 lw R1 R0 bit1 add R2 R2 R1 lw R1 R0 bit2 add R2 R2 R1 lw R1 R0 bit3 add R2 R2 R1 lw R1 R0 bit4 add R2 R2 R1 lw R1 R0 bit5 add R2 R2 R1 lw R1 R0 bit6 add R2 R2 R1 lw R1 R0 bit7 add R2 R2 R1 lw R1 R0 bit8 add R2 R2 R1 lw R1 R0 bit9 add R2 R2 R1 lw R1 R0 bit10 add R2 R2 R1 lw R1 R0 bit11 add R2 R2 R1 lw R1 R0 bit12 add R2 R2 R1 lw R1 R0 bit13 add R2 R2 R1 lw R1 R0 bit14 add R2 R2 R1 lw R1 R0 bit15 add R2 R2 R1 lw R1 R0 bit16 add R2 R2 R1 lw R1 R0 bit17 add R2 R2 R1 lw R1 R0 bit18 add R2 R2 R1 lw R1 R0 bit19 add R2 R2 R1 lw R1 R0 bit20 add R2 R2 R1 lw R1 R0 bit21 add R2 R2 R1 lw R1 R0 bit22 add R2 R2 R1 lw R1 R0 bit23 add R2 R2 R1 lw R1 R0 bit24 add R2 R2 R1 lw R1 R0 bit25 add R2 R2 R1 lw R1 R0 bit26 add R2 R2 R1 lw R1 R0 bit27 add R2 R2 R1 lw R1 R0 bit28 add R2 R2 R1 lw R1 R0 bit29 add R2 R2 R1 lw R1 R0 bit30 add R2 R2 R1 lw R1 R0 bit31 add R2 R2 R1 addi R2 R2 0x1 * Zero in ACC (test carry out) addi R2 R0 0xffff lw R1 R0 bit0 sub R2 R2 R1 lw R1 R0 bit1 sub R2 R2 R1 lw R1 R0 bit2 sub R2 R2 R1 lw R1 R0 bit3 sub R2 R2 R1 lw R1 R0 bit4 sub R2 R2 R1 lw R1 R0 bit5 sub R2 R2 R1 lw R1 R0 bit6 sub R2 R2 R1 lw R1 R0 bit7 sub R2 R2 R1 lw R1 R0 bit8 sub R2 R2 R1 lw R1 R0 bit9 sub R2 R2 R1 lw R1 R0 bit10 sub R2 R2 R1 lw R1 R0 bit11 sub R2 R2 R1 lw R1 R0 bit12 sub R2 R2 R1 lw R1 R0 bit13 sub R2 R2 R1 lw R1 R0 bit14 sub R2 R2 R1 lw R1 R0 bit15 sub R2 R2 R1 lw R1 R0 bit16 sub R2 R2 R1 lw R1 R0 bit17 sub R2 R2 R1 lw R1 R0 bit18 sub R2 R2 R1 lw R1 R0 bit19 sub R2 R2 R1 lw R1 R0 bit20 sub R2 R2 R1 lw R1 R0 bit21 sub R2 R2 R1 lw R1 R0 bit22 sub R2 R2 R1 lw R1 R0 bit23 sub R2 R2 R1 lw R1 R0 bit24 sub R2 R2 R1 lw R1 R0 bit25 sub R2 R2 R1 lw R1 R0 bit26 sub R2 R2 R1 lw R1 R0 bit27 sub R2 R2 R1 lw R1 R0 bit28 sub R2 R2 R1 lw R1 R0 bit29 sub R2 R2 R1 lw R1 R0 bit30 sub R2 R2 R1 lw R1 R0 bit31 sub R2 R2 R1 addi R2 R2 -1 * -1 in ACC (test carry out) lw R1 R0 adr6 jr R1 *------------------------------------------------------------------* * Test6: ALU: Or, And, Xor, TestSet *------------------------------------------------------------------* pc = 0x00000600 test6: dc 0xc0000006 * Special-NOP lw R2 R0 mask0 lw R1 R0 mask0 or R2 R2 R1 * acc -> 0x00000000 lw R1 R0 mask8 or R2 R2 R1 lw R1 R0 mask16 or R2 R2 R1 lw R1 R0 mask24 or R2 R2 R1 lw R1 R0 mask32 or R2 R2 R1 * acc -> 0xffffffff lw R2 R0 mask32 lw R1 R0 mask32 and R2 R2 R1 * acc -> 0xffffffff lw R1 R0 mask24 and R2 R2 R1 lw R1 R0 mask16 and R2 R2 R1 lw R1 R0 mask8 and R2 R2 R1 lw R1 R0 mask0 and R2 R2 R1 * acc -> 0x00000000 lw R2 R0 maska5 lw R1 R0 maska5 xor R2 R2 R1 * acc -> 0x00000000 lw R2 R0 mask5a lw R1 R0 mask5a xor R2 R2 R1 * acc -> 0x00000000 lw R2 R0 maska5 * acc -> 0xa5a5a5a5 lw R1 R0 mask5a xor R2 R2 R1 * acc -> 0xffffffff lw R1 R0 maska5 xor R2 R2 R1 * acc -> 0x5a5a5a5a lw R1 R0 mask5a xor R2 R2 R1 * acc -> 0x00000000 addi R1 R0 0x0 sgti R2 R1 0 seqi R2 R1 0 sgei R2 R1 0 slti R2 R1 0 snei R2 R1 0 slei R2 R1 0 sgti R2 R1 1 seqi R2 R1 1 sgei R2 R1 1 slti R2 R1 1 snei R2 R1 1 slei R2 R1 1 sgti R2 R1 -1 seqi R2 R1 -1 sgei R2 R1 -1 slti R2 R1 -1 snei R2 R1 -1 slei R2 R1 -1 addi R1 R0 1 sgti R2 R1 0x0 seqi R2 R1 0x0 sgei R2 R1 0x0 slti R2 R1 0x0 snei R2 R1 0x0 slei R2 R1 0x0 addi R1 R0 -1 sgti R2 R1 0x0 seqi R2 R1 0x0 sgei R2 R1 0x0 slti R2 R1 0x0 snei R2 R1 0x0 slei R2 R1 0x0 lw R1 R0 adr7 jr R1 *------------------------------------------------------------------* * Test7: Branch / JALR *------------------------------------------------------------------* pc = 0x00000700 test7: dc 0xc0000007 * Special-NOP addi R1 R0 0x0 * Branch-Test bnez R1 error7 * invalid branch condition beqz R1 test7b * branch forward lw R1 R0 adr7 jr R1 test7a: beqz R1 test7c * branch forward test7b: beqz R1 test7a * branch backward nop nop lw R1 R0 adr7 jr R1 test7c: addi R1 R0 0x1 beqz R1 error7 * invalid branch condition bnez R1 test7e * branch forward lw R1 R0 adr7 jr R1 test7d: bnez R1 test7f * branch forward test7e: bnez R1 test7d * branch backward nop nop lw R1 R0 adr7 jr R1 error7: lw R1 R0 adr7 jr R1 test7f: addi R1 R0 jlink * JALR-Test jalr R1 beqz R0 -1 * Stop, if JALR failed jlink: addi R31 R31 0x1 xor R1 R31 R1 * compare R31 beqz R1 test7g beqz R0 -1 * Stop, if R31 wrongly set test7g: lw R1 R0 adr8 jr R1 *------------------------------------------------------------------* * Test8: RAM Test (optional) *------------------------------------------------------------------* pc = 0x00000800 test8: dc 0xc0000008 * Special-NOP lw R30 R0 RAM * R30 := Address of RAM lw R1 R0 RESA lw R2 R30 0x0 * read from M[0x800000] xor R2 R2 R1 * if (M[0x800000]=="RESA") beqz R2 start * then jump to user program bnez R2 ramtst * else perform memory test *------------------------------------------------------------------* ramtst: addi R1 R0 0x0 * Test of first address of RAM sw R1 R30 0x0 * 0x00000000 -> hilf lw R2 R30 0x0 xor R2 R2 R1 bnez R2 error8 addi R1 R0 0xffff sw R1 R30 0x0 * 0xffffffff -> hilf lw R2 R30 0x0 xor R2 R2 R1 bnez R2 error8 addi R1 R0 0x1 * Test of each single bit loop8: sw R1 R30 0x0 * Powers of 2 -> hilf lw R2 R30 0x0 xor R2 R2 R1 bnez R2 error8 slli R1 R1 bnez R1 loop8 test8a: lw R1 R0 ramadr * Test of each single RAM cell lw R2 R0 ramend loop8a: sw R1 R30 0x0 sub R3 R1 R2 beqz R3 test8b sw R1 R1 0x0 addi R1 R1 0x1 beqz R0 loop8a test8b: lw R1 R0 ramadr loop8b: sw R1 R30 0x0 sub R3 R1 R2 beqz R3 test8c lw R3 R1 0x0 * Compare memory contents xor R3 R3 R1 bnez R3 error8 sw R0 R1 0x0 * Erase memory addi R1 R1 0x1 beqz R0 loop8b error8: beqz R0 error8 * Endless loop test8c: sw R0 R30 0x0 * Test successful stop8: beqz R0 stop8 * Endless loop *------------------------------------------------------------------* * Start user program *------------------------------------------------------------------* start: lw R30 R0 RAM * Load start address of RAM lw R1 R0 USER * Load start address of user program jalr R1 * Jump to user program ende: beqz R0 ende *------------------------------------------------------------------*