21/2/99

Deadlines for submissions:

Ex 4: 	28/2/99
Ex 5+6: 28/3/99

During March (except for 21-24/3), please contact Dror if you want 
to use the lab.
During 21-24/3, please contact Guy or Danny. 


18/2/99

Fixed DLXSIM.
Joerg Fischer fixed the mistake with the comparisons (numbers
were treated as unsigned).
The new version is downloadable from the course's home page.

15/2/99

Grading policy: 

Assignment 	topic			weight 
#1		simple bus interface	 8%
#2		counter+monitor		 8% 
#3		read/write machine	20%
#4		load/store machine	20%
#5		test vectors		 4%
#6		DLX+software		20%
quizzes (5 written, 1 oral)		20%


28/1/99

A new library lablib2 has been prepared for your use.
This library contains a full slave monitor macro called
Monitor2. Monitor2 is a complete monitor slave with a 
logic analyzer and 5 inputs of 32 bits each from the
application. A diskette with this library is available for 
every group.

The addresses of the monitor slave are given in the
config.txt file which is listed below:

"This file describes the Monitor Slave Adresses 
"and the Write_Application bits and addresses

"---------------------------------------------------
" Monitor Slave;
"=================
"
" Bits 7..5 of the command reg determine which
" input id monitored (captured) by the Logic Analyzer:
" command=0x00 => signals
" command=0x20 => status
" command=0x40 => analyzer
" command=0x60 => command
" command=0x80 => rdbk0
" command=0xa0 => rdbk1
" command=0xc0 => rdbk2
" command=0xe0 => rdbk3

" The RESACTRL program may access the same inputs
" since the output of the mux is connected to the
" slave data out bus (= SDO[31:0])
c signals  0x80
c status   0x81
c analyzer 0x82
c command  0x83
c rdbk0    0x84
c rdbk1    0x85
c rdbk2    0x86
c rdbk3    0x87
"-----------------------------------------------------


14/1/99

1. The stop signal equals stop= !step_en

2. Guideline 3(i) is overridden by handout #5 in which
you are requested to output the state of the control 
to enable testing.

3. There are some gaps in figures 3 and 4:

	(a) Be sure to avoid an extra memory access that
	might be caused by the mr or mw signals (if they are
	left active too long).

	(b) Make sure you activate the clock enable of the
	MDR so that it samples the DI bus in the right cycle. 
	A (dirty) way to solve it is to use the ack signal although 
	it is not depicted like that in the figures. 

10/1/99

Handout #4 has 4 errors listed below. The revised version
is placed in the course's web page.

1. Handout #4: page 11, question 6. Should be: Tables 4 & 5.

2. Figure 1 in handout #4: Names of data_in driver and data_out
driver should be switched.

3. In load and store instructions, the imm constant should be
sign extended.

4. Arrow in Figure 3 for the Ao[0:31] is in the wrong direction.

7/1/99

1. The encoding of an R-type instruction is
IR[31:26]=000000.