Research and Professional Experience

1977-1983 Electrical Engineering Department, Technion - Israel Institute of Technology: Research in physics and technology of infrared quantum detectors: photo-conductive devices, mosaic focal plane arrays, and integration in the focal plane. Research in narrow band-gap semiconductors for infrared sensing applications, HgCdTe (1977-1983) and InSb (1982-1983). Noise in quantum detectors, low noise amplifiers. HgCdTe for high temperature applications. Experience in semiconductor technology: process simulation, layout patterning, mask generation, processing, and testing.

1983 to 1986: Electronics Research Laboratory, University of California, Berkeley: Research Associate Engineer. Research on VLSI process development.

1983 - 1986: Post doctoral research: Collaborated in the construction and installation of the microfabrication facility at the University of California, Berkeley. Development and processes design of the ABC-MOS (Advanced Berkeley, CMOS), a 9-mask, 1.25 µm design rules, n-well process for both digital and analog applications. Research on advanced technology for VLSI: trench isolation technology, planarization methods (SOG) and the influence of hydrogen on dopants diffusion in SiO2.

1985 - 1986 Lift-off processes, spin-on technologies and application of electrochemical processes like porous oxide for selective isolation. Supervised 5 Ph.D. students in the following topics: Si epitaxy, 2D flow and stress in thin-films, holographic methods for photolithography, and expert systems for VLSI.

1986 - 1989 Technion - Israel Institute of Technology, Dept. of Electrical Engineering:

a) Research on low temperature MOS technology and devices:

b) Advanced VLSI technologies: Multi metal processes; planarization and Via-contacts methodologies, spin-on-glass, fully planarized metallization, Deep UV lithography, materials and dry-development.

c) Focal plane integrated infra-red sensor arrays.

1989 to present - Cornell University, School of Electrical Engineering: Research on nanoelectronics process technology and devices for integrated circuits and micromachining applications:

a) Nanoline interconnect technology and multilevel metallization systems:

• Electroless copper technology (Metals and dielectrics)
• Inspection of sub-half micron interconnect systems (Electrical, Optical, X-Ray, etc.)

• Spin on glass materials for ULSI applications

b) Silicon-Germanium quantum well MOS technology
 

line

Return to:

[Yosi Shaham's home page | Department of Electrical Engineering - Physical Electronics | Faculty of Engineering ]

line

Please send comments or questions about this page to the: < Maintainer@eng.tau.ac.il >


Last modified: January 1999.